1. Field of the Invention
This invention relates generally to random access memory (RAM) circuits. More particularly, this invention relates to static RAM circuits. Even more particularly, this invention relates to integrated nonvolatile static RAM (NVSRAM) circuits where the nonvolatile memory element is a floating gate tunnel oxide (FLOTOX) nonvolatile memory device.
2. Description of Related Art
In the semiconductor industry, generally, there are two important kinds of CMOS memories such as “volatile” and “non-volatile”. The “volatile” memory (VM), in which the stored data would not be retained when its low-voltage VDD power supply is removed or shut down. The VM memories include Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). The SRAM has the largest cell size because it is formed from six (6) CMOS transistors, i.e. 2 PMOS and 4 NMOS.
The DRAM conversely has a small cell size because it has only one NMOS switching transistor connected in series with a capacitor that is used to store the charge of data. The feature size of both SRAM and DRAM volatile memories allow low-voltage CMOS devices that have a very fast read and write speed in 20 ns range. During repeat read and write operation, SRAM does not need refresh cycle as with a DRAM.
The SRAM, as is well known in the art, consists of a bistable transistor flip-flop or latching circuit. Referring to FIGS. 1a and 1b, the inverters I1 5 and I2 10 are coupled such that the output of the inverter I1 5 is connected to the input of the inverter I2 10 and the output of the inverters I2 10 is connected to the input of the inverter I1 5 to form the bistable latch. The access transistor Ma1 15 has a drain terminal connected to the input of the inverter I1 5 and the output of the inverter I2 10 and a source terminal connected to the bit line BL 25. The access transistor Ma2 20 has a drain terminal connected to the input of the inverter I2 10 and the output of the inverter I1 5 and a source terminal connected to the bit line BL 30. The gates of the access transistors Ma1 15 and Ma2 20 are connected to the word line WL 35 to receive the activation signals for accessing the memory cell.
In operation, the bit lines BL 25 and BL 30 are precharged respectively to the data to be written or read from the memory cell. The word Line WL 35 is set to a voltage level sufficient to activate the access transistors Ma1 15 and Ma2 20 and the digital signal representative of the binary data to be written to or read from the memory cell is transferred to or from the memory cell.
The inverter I1 5 consists of the n-type MOS transistor Mn1 9 and the p-type MOS transistor Mp1 7 configured as the well known CMOS inverter. Similarly the inverter I2 10 consists of the n-type MOS transistor Mn2 13 and the p-type MOS transistor Mp2 11 also configured a CMOS inverter. The gates of the n-type MOS transistor Mn1 9 and the p-type MOS transistor Mp1 7 are connected to the common drain connection of the n-type MOS transistor Mn2 13 and the p-type MOS transistor Mp2 11 and the gates of the n-type MOS transistor Mn2 13 and the p-type MOS transistor Mp2 11 are connected to the common drain connection of the n-type MOS transistor Mn1 9 and the p-type MOS transistor Mp1 7. This forms the cross-connection to create the bistable flip-flop. The sources of the gates of the n-type MOS transistor Mn1 9 and the p-type MOS transistor Mp1 7 are connected to the common drain connection of the n-type MOS transistors Mn2 13 and Mn1 9 are connected to the ground reference voltage source and the sources of the p-type MOS transistors Mp1 7 and Mp2 11 are connected to the power supply voltage source VDD.
As stated above, the bit lines BL 25 and BL 30 are precharged for performing desired writing and read from the SRAM cell. For instance if the digital signals representing a binary 1 are to be written to the SRAM cell, the bit line BL 25 is set to the voltage of the power supply voltage source VDD less a voltage threshold VT of an MOS transistor and the bit line BL 30 is set to essentially the ground voltage level. The word Line WL 35 is set to a voltage level sufficient to activate the access transistors Ma1 15 and Ma2 20. The digital signal representing the binary “1” turns on the n-type MOS transistor Mn2 13 and turns off the p-type MOS transistor Mp2 11. The complementary binary “0” present at the bit line BL 30 turns on the p-type MOS transistor Mp1 7 and turns off the n-type MOS transistor Mn1 9, thus setting the flip-flop For reading the SRAM cell, the bit lines BL 25 and BL 30 are precharged to a level approximately equal to one half of the voltage level of the power supply voltage source VDD and the word Line WL 35 is set to the voltage level sufficient to activate the access transistors Ma1 15 and Ma2 20. The digital signals present at the drains of the n-type MOS transistor Mn1 9 and the p-type MOS transistor Mp1 7 are transferred to the bit line BL 25 and the digital signals present at the n-type MOS transistor Mn2 13 and the p-type MOS transistor Mp2 11 is transferred to the bit line BL 30. The bit lines BL 25 and BL 30 are connected to a bit line sense amplifier to regenerate the binary data.
The “non-volatile” memory (NVM), in which the stored data would not be corrupted and normally is retained for more than 20 years even after the power supply voltage source (VDD) is completely disconnected. Today, there are many different kinds of NVM memories aimed for different applications. For example, the most popular NVM today is NAND flash with a very small cell size of about 0.5 T cell size of 4λ2 (λ2 being the smallest area capable for a given semiconductor process) and is generally used to store huge blocks of data necessary for audio and video serial applications. The highest available memory density is up to 16 Gb and is currently made of 45 nm in 2007. The second largest revenue of NVM is NOR flash with one-transistor cell of about 10λ2 and is used to store the program code. Today, the highest available NOR memory density is about 2 Gb in the market place and is made of 70 nm in 2007. The third type of NVM is 2-transistor floating gate tunnel oxide (FLOTOX) EEPROM with cell size of about 80λ2. Currently, the density of EEPROM is around 1 Mb only and is used in byte-alterable application. Unlike NAND and NOR Flash Ram that only allows big-block data alterability, EEPROM can achieve the largest number of program/erase (P/E) cycles. In the current design, the EEPROM is capable of 1 M P/E cycles when accomplished in units of bytes for small data change applications.
There are several disadvantages for NVM. The on-chip, high-voltage devices, charge-pump circuits, and the complicated double-polycrystalline silicon cell structure are required for the basic erase and program operations. Secondly, these NVM cell's program and erase operations cannot be performed as fast as its read operation. Typically, the required Program and Erase operation speed for the above NVM memories ranges from few hundred μs to few ms but only requires less than 50 ns for Read operation. In EEPROM terminology, Write means program plus erase operation. Typically, the write takes much longer than read so that it becomes the bottleneck in many applications.
The data retained in an SRAM memory cell is volatile, in that any interruption of the power supply voltage source causes a loss of the data. An alternative to the volatile SRAM is the nonvolatile RAM. One nonvolatile RAM consists of a floating gate transistor which has a charge placed on a floating gate to modify the voltage threshold VT of the floating gate transistor that indicates the state of the binary data retained in the nonvolatile RAM cell. The cell structure and application of the nonvolatile RAM is well known in the art. The nonvolatile RAM has three classifications the Electrically Programmable Read Only Memory (EPROM), Electrically Erasable and Programmable Read Only Memory (EEPROM), and the flash Electrically Erasable and Programmable Read Only Memory (Flash). The EPROM is programmed by electrically forcing charge to the floating gate. Ultra-violet light is employed to eliminate (erase) the electrical charges of the programming from the floating gate of the EPROM. During EPROM program operation, in addition to a low-voltage power supply (VDD), an external high-voltage programming power supply (VPP) of about 12V is used. With a sealed package, UV-light cannot reach floating-gate, thus the erase operation is blocked and the EPROM is considered a One Time Programmable (OTP) EPROM. If the sealed OTP is changed to sealed Flash, then both erase and program operations can be performed electrically and repeatedly in system without the overheads of UV-light exposure and the external VPP programmer due to Flash's on-chip charge pump that can generate high voltage internally.
The Flash type nonvolatile RAM offers a medium read speed of around 50 ns but a very slow write speed of a few milliseconds (ms). The reason for such a slow write speed in today's flash memory cells are mainly due to its slow program and erase schemes based on device Fowler-Nordheim tunneling. The Fowler-Nordheim tunneling effect allows the electrons to be injected into or removed from flash's floating gate that is used to store the data. In order to have a successful Fowler-Nordheim tunneling effect, the electric field across the tunneling oxide has to be maintained larger than 10V/cm. That is the reason why most of the flash memory requires a charge pump to generate on-chip high-voltage for erase and program operations.
FIG. 2a illustrates the schematic circuit for a 2-transistor, CMOS, FLOTOX EEPROM cell of the prior art. The EEPROM cell of the prior art includes of two transistors 100 and 105. The select transistor, N1 100 is a Polysilicon NMOS device with its gate connected to a select gate signal SG 110. The source of the select transistor is connected to the drain of the floating gate tunnel oxide (FLOTOX) EEPROM cell N2 105. The FLOTOX EEPROM cell N2 105 is a double polysilicon floating gate device. A first layer of polysilicon is the floating-gate 107 that is used to store the charges representing the binary “0” and binary “1” of the stored data. The second layer of the polysilicon is a control gate 108 that is connected to the word line WL 115. The drain of the select transistor N1 100 is connected to a vertical and global metal bit line BL 120. The source of the EEPROM cell N2 105 is connected to a common source line SL 125.
FIGS. 2b and 2c illustrate the physical layout for the two-transistor FLOTOX EEPROM circuit of FIG. 2a of the traditional two-transistor FLOTOX EEPROM cell as formed in a substrate 150. A first layer polysilicon conductor forms the select gate 110 and runs horizontally in parallel with a second level polysilicon conductor that forms the word line WL 115. The overlapping area of a first layer polysilicon conductor 102 and N+ active layers 130 and 135 form a polysilicon NMOS select transistor N1 100. The drain region 130 of the select transistor 100 has a half-contact 122 for the connection with the global metal bit line BL 120. The FLOTOX EEPROM cell N2 105 is a double-poly floating gate device and is formed above the N+ layers 135 and 140. The first layer polysilicon conductor 107 forms the floating gate and is placed below the second layer polysilicon conductor 108 that forms the control gate. A square box of a tunnel window layer of TOW 145 has about 100 Å thickness to allow Fowler-Nordheim programming and erasing during the normal write operation of the FLOTOX EEPROM cell N2 105. In traditional FLOTOX EEPROM cell, a write operation is comprised of two self-timed Fowler-Nordheim tunneling steps. The first step is Fowler-Nordheim tunneling erase and then follows the second step of FN tunneling program. In traditional EEPROM write operation, the erase operation takes about 0.5 ms and program also takes about same 0.5 ms typically. The FLOTOX EEPROM cell's N2 105 threshold voltage (Vt) will be increased to around +2V with data of “1” after erase. But after the subsequent Fowler-Nordheim program operation, the selected FLOTOX EEPROM cell's N2 105 is programmed by decreasing the threshold voltage (Vt) to about −2V with data of a binary “0”. The deselected programmed cell's threshold voltage (Vt) will remain unchanged at +2V with data of a binary “1”.
U.S. Pat. No. 5,488,579 (Sharma, et al.) details a nonvolatile SRAM cell that includes a six-transistor SRAM cell and a three-transistor nonvolatile memory portion. The nonvolatile memory portion is connected to one storage node of the SRAM cell portion.
U.S. Pat. No. 6,097,629 (Dietrich, et al.) describes a non-volatile, static random access memory (nvSRAM) device that is capable of high speed copying of the data in the static random access portion of the device into the non-volatile portion of the device after the detection of possible loss of power. This is accomplished by preparing the non-volatile portion for receiving a bit of data from the SRAM portion before the possible loss of power is detected, i.e., pre-arming the device. The pre-arming is accomplished by erasing the non-volatile portion immediately after power has been provided to the device and data from the non-volatile portion has been copied into the SRAM in a recall operation.
U.S. Pat. No. 7,280,397 (Scheuerlein) provides a shadow RAM or “non-volatile SRAM” memory cell. The memory cell includes a pair of cross-coupled devices disposed on a first device layer and defining a pair of internal cross-coupled nodes, and a pair of non-volatile storage devices disposed on a second device layer above or below the pair of cross-coupled devices and coupled to the cross-coupled nodes.
U.S. Patent Application 2008/0151643 (Ashokkumar, et al.) and U.S. Patent Application 2008/0151654 (Allan, et al.) illustrate a non-volatile SRAM cell that has a volatile portion and a non-volatile portion. Each tri-gate structure in the non-volatile portion has a recall transistor, a store transistor and at least one SONOS transistor. The volatile portion has an SRAM cell comprising six transistors with two back-to-back inverters forming the latch and two pass transistors gated by the word-line signal which connect the bit-line true to the data true node of the latch and the bit-line complement to the data complement node of the latch, a word line, a node supplying power to the SRAM cell and a bit line pair with a first bit line and a second bit line. The first and second SONOS transistors are programmed so that the first tri-gate having the first SONOS transistor is configured in an erased condition and the second tri-gate structure having the second SONOS transistor is configured in a programmed condition. The volatile portion is isolated from the non-volatile portion by turning off a first store transistor in the first tri-gate structure and turning off a second store transistor in the second tri-gate structure.
U.S. Patent Application (2008/0158981) Johal, et al. describes a non-volatile SRAM cell that has a volatile portion and a non-volatile portion and provides a method and apparatus for on chip sensing of SONOS threshold voltage VT window in the non-volatile portion.
There is a need to have a random access memory that offers the same fast read and write speed as conventional SRAM in 10 ns range and while retaining the non-volatility of flash to retain its data when power loss occurs.